Daily Snippet: 3rd Aug 2016

  • As per discussions with mithro, changing module definitions as defined in the block diagram
  • link
  • Trying to fix some errors in the implementation of pixel clock, here only one PLL is used and some error is appearing in MAP phase of Xilinx Build process.
  • Need to figure out how to correctly connect shared PLL across two HDMI_OUTs
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