Final Snippet: 21 August 2016

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Daily Snippet: 7th August 2016

Week 11: Weekly Report

I have been trying to fix the errors from the last week and complete the Single Output Mixer Pipeline. This cover week 11, the week from 29th July to 5th August.

Major tasks accomplished this week:

  • Add extra DMA block to one HDMI_Out such that the output is synchronized and alignment errors are corrected.
  • In the process read up a whole bunch of documentation on implementation of VGA Core from MIgen docs, and the HDMi_Out core is based on a similar kind of connections https://migen.readthedocs.io/en/latest/casestudies.html
  • Changed layout and instantiated several modules to get two DMA engine blocks per HDMI_OUT
  • Block diagrams currently being updated, current ones in the doc https://docs.google.com/document/d/1g1c2IwCVxVzSHWdXbZ746HP-fnM4y1WqFuBZNkLi5mw/edit
  • Initially doing this for two outputs, but failing to make this work after several Xilinx specific errors in MAP stage.
  • Fixed the errors being caused, those were because of incorrect use of

    platform.request("hdmi_out", 1), because these pins aren’t used.
  • Current status, DMA engine is supposed to take two base address for two video streams to be mixed, from
hdmi_out0_fi_base0_write() 

hdmi_out0_fi_base1_write()
  • In this hdmi_out0_fi_base1_write, somehow doesn’t work.

 

Next Week’s task:

Finish everything asap!

Daily Snippet: 4th Aug 2016

  • Was getting some errors in the map phase for process flow, so difficult to debug and correct
  • After several changes in PLL clock setup for HDMI_OUTs, fixed the error, this was because of unnecessary usage of platform.rquest() for HDMI_OUT_1 pads.
  • Testing the mixer using new DMA setup, with just one HDMI_OUT
  • For HDMI_OUT, hdmi_out0_fi_base0_write, working fine, but hdmi_out0_fi_base1_write(), is not functioning at all, hence not able to mix the inputs currently