- Complete the code, adding dynamic fades
- Link to video of working fades
- Final Documentation being updated here
- This will also serve as the final PR link which is supposed to be submitted as the final evaluation for GSoC.
- Link to final report https://shashankgangrade.wordpress.com/gsoc-final/
- Testing of reworked HDMI_OUT Core
- Problems with DMA engine and some random timing problems
This is the final week of GSoC! Need to finish everything ASAP. Instead of putting a report for this week, I will put up a complete final report which covers everything I did during these three months. Keep look out for that!
- Continuing work on HDMI OUT
- Now aiming at P4 instead of P2 diagram in the mixer block doc, due to some clocking problems
- TA meeting today
- Made a separate branch for HDMI_Out rework
- Mixer block diagram has direct connections
- Fixing some error in compilation
- Trying to fix to timing Syncronization problem while reading from two DMA sources.
- As per suggetions from rohitksingh, need to an Combinator Module
- Added and tested the static mixing link
- Also tested dynamic fading by changing multiplier value from firmware
- Next step is to to rework gateware like mentioned in this block diagram
I have been trying to fix the errors from the last week and complete the Single Output Mixer Pipeline. This cover week 11, the week from 29th July to 5th August.
Major tasks accomplished this week:
- Add extra DMA block to one HDMI_Out such that the output is synchronized and alignment errors are corrected.
- In the process read up a whole bunch of documentation on implementation of VGA Core from MIgen docs, and the HDMi_Out core is based on a similar kind of connections https://migen.readthedocs.io/en/latest/casestudies.html
- Changed layout and instantiated several modules to get two DMA engine blocks per HDMI_OUT
- Block diagrams currently being updated, current ones in the doc https://docs.google.com/document/d/1g1c2IwCVxVzSHWdXbZ746HP-fnM4y1WqFuBZNkLi5mw/edit
- Initially doing this for two outputs, but failing to make this work after several Xilinx specific errors in MAP stage.
- Fixed the errors being caused, those were because of incorrect use of
platform.request("hdmi_out", 1), because these pins aren’t used.
- Current status, DMA engine is supposed to take two base address for two video streams to be mixed, from
- In this hdmi_out0_fi_base1_write, somehow doesn’t work.
Next Week’s task:
Finish everything asap!
- Weekly GSoC review
- Figured out problems in DMA time syncronization which needs to solved
- TA meeting for the course with Professor and RAs
- Was getting some errors in the map phase for process flow, so difficult to debug and correct
- After several changes in PLL clock setup for HDMI_OUTs, fixed the error, this was because of unnecessary usage of platform.rquest() for HDMI_OUT_1 pads.
- Testing the mixer using new DMA setup, with just one HDMI_OUT
- For HDMI_OUT, hdmi_out0_fi_base0_write, working fine, but hdmi_out0_fi_base1_write(), is not functioning at all, hence not able to mix the inputs currently
- As per discussions with mithro, changing module definitions as defined in the block diagram
- Trying to fix some errors in the implementation of pixel clock, here only one PLL is used and some error is appearing in MAP phase of Xilinx Build process.
- Need to figure out how to correctly connect shared PLL across two HDMI_OUTs